Seven Segment Tile

Here is the Top level AHDL Seven_segment.py

Shown below is the Tile example class example we derived from the BlackIce Mx nMigen examples for the seven segment tile.

from amaranth import *
from IceLogicDeck import *
from Tiles.seven_seg_tile import SevenSegController, tile_resources

TILE = 1


class SevenSegExample(Elaboratable):
    def elaborate(self, platform):
        # Add 7-segment controller
        m = Module()
        m.submodules.seven = seven = SevenSegController()

        # Get pins
        seg_pins = platform.request("seven_seg_tile")
        leds7 = Cat([seg_pins.a, seg_pins.b, seg_pins.c, seg_pins.d,
                     seg_pins.e, seg_pins.f, seg_pins.g])

        # Timer
        timer = Signal(40)
        m.d.sync += timer.eq(timer + 1)

        # Connect pins
        m.d.comb += [
            leds7.eq(seven.leds)
        ]

        # Set pins for each digit to appropriate slice of time to count up in hex
        for i in range(3):
            # Each digit refreshed at at least 100Hz
            m.d.comb += seg_pins.ca[i].eq(timer[17:19] == i)

            with m.If(seg_pins.ca[i]):
                m.d.comb += seven.val.eq(timer[((i - 3) * 4) - 5:((i - 3) * 4) - 1])

        return m


if __name__ == "__main__":
    platform = IceLogicDeckPlatform()
    platform.add_resources(tile_resources(TILE))
    platform.build(SevenSegExample(), do_program=True)

The Seven Segment Tile Driver

The tile driver abstracts the tile resource pinouts handling the low level Hex->7-segment encoding.

from typing import List

from amaranth import *
from amaranth.build import *

PINMAP = {"a": "6", "b": "8", "c": "12", "d": "10", "e": "7", "f": "5", "g": "4", "dp": "9", "ca": "3 2 1"}


def tile_resources(tile: int) -> List:
    signals = [
        Subsignal(signal,
                  Pins(pin, invert=True, dir="o", conn=("tile", tile)),
                  Attrs(IO_STANDARD="SB_LVCMOS")
                  ) for signal, pin in PINMAP.items()
    ]

    return [Resource("seven_seg_tile", 0, *signals)]


class SevenSegController(Elaboratable):
    def __init__(self):
        self.val = Signal(4)
        self.leds = Signal(7)

    def elaborate(self, platform):
        m = Module()

        table = Array([
            0b0111111,  # 0
            0b0000110,  # 1
            0b1011011,  # 2
            0b1001111,  # 3
            0b1100110,  # 4
            0b1101101,  # 5
            0b1111101,  # 6
            0b0000111,  # 7
            0b1111111,  # 8
            0b1101111,  # 9
            0b1110111,  # A
            0b1111100,  # B
            0b0111001,  # C
            0b1011110,  # D
            0b1111001,  # E
            0b1110001  # F
        ])

        m.d.comb += self.leds.eq(table[self.val])

        return m